The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component or line that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In one example, advanced lithography patterning technologies are implemented to form various patterns, such as gate electrodes and metal lines, on semiconductor wafers. A lithography patterning technologies include coating a resist material on the surface of a semiconductor wafer.
The existing resist coating method, such as spin coating, forms the resist material on all regions of a wafer including edges of the wafer, even to the backside surface of the wafer. The resist material on the edges and the backside surface of the wafer during the coating process and subsequent processes (such as developing) leads to various contamination-related problems and concerns, such as contaminating the coater chuck or the track. Accumulation of the resist material on the edges of the wafer will disturb patterning stability on the wafer edge and causes erroneous leveling readings during the lithography process. For examples, the presence of the resist material on the bevel and backside not only increases the probability of high hotspot but also has the potential to contaminate subsequent processing tools. In other examples, existing coating process has high resist residual at wafer edges and bevel, which may induce resist peeling and result in poor yield. Various methods are used or proposed to address the issues, such as edge bead rinse, backside rinse and additional coating. However, the undesired hump was created by edge bead rinse and backside rinse, which is potential defect source in the following processes. In other cases, the additional coating further introduces contaminations to wafers and lithography system, or has additional efficiency and effectiveness concerns to manufacturing throughput. Accordingly, it may be desirable to provide a system and a method of utilizing thereof absent the disadvantages discussed above.